To evaluate the performance of input/output I/O circuits within an integrated circuit, it is desirable to measure the delay between the input and the output of such a circuit. The delay of an I/O circuit is an important parameter as it affects the overall timing of the integrated circuit.
However, numerous difficulties are present to measure the delay of an I/O cell as it is usually not possible to access the input terminals of such an I/O circuit because these terminals are typically connected to a core side of the integrated circuit.
U.S. Pat. No. 6,563,335 B2 discloses a test method for semiconductor device to evaluate the delay of an input/output I/O circuit. A delay evaluation circuit is arranged in a basic cell area of the chip core portion. A test cell comprises a first delay circuit with several stages of inverters connected by an interconnect layer and a delay evaluation switching circuit. The test cell can be switched between a first measurement mode for measuring a delay between the input of the I/O circuit and the output I/O circuit and a second measurement mode for measuring a delay between the input and the output of the I/O circuit via a first delay circuit. However, according to this method, a test cell needs to be included on the semiconductor device consuming a significant amount of the chip area on the semiconductor chip.